Hi, my name is

Arya Raeesi.

M.Sc. student in Electronic Systems Design and Innovation at NTNU, including a one-year graduate exchange at UC Berkeley EECS. Experience from the NASA Small Explorers (SMEX) Program, Qualcomm (incoming), the Cornell Natural Language Processing Group, Sony Europe, and Nordic Semiconductor, with projects involving institutions across North America, Europe, and Asia. My work sits at the intersection of machine learning systems and hardware design: LLM inference and serving, evaluation and auditing of language models, and low-power inference accelerators.

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I am grateful to the following institutions that have supported, hosted, or funded the research initiatives, and projects I have contributed to acknowledgements →

01. Projects

Research Engineering

▸ Ongoing

AI · EE

Aug 2026 – Dec 2026

RISC-V ML Inference Co-Processor for Ultra-Low-Power Wireless SoCs

Extending a custom SystemVerilog pre-processing accelerator for ML into a dedicated inference co-processor, unifying pre-processing and inference in a single peripheral unit to support a parallel RISC-V ML ISA extension. Targeting on-device ML for ultra-low-power wireless SoCs.

Affiliation

Nordic Semiconductor ASA

Partners

Keywords

SystemVerilog
RISC-V
ISA Extensions
Hardware Accelerators
ML Inference
On-Device ML
RTL Design
Ultra-Low-Power Design
Hardware-Software Co-Design

AI · CS

Jul 2026 – Ongoing

Deleted but Not Gone: Auditing Erasure in Memory-Augmented Language Models

Extending my causal audit framework for machine unlearning [arXiv:2607.00605] to Co-LMLM's dense external memory, in direct collaboration with its authors. HALO runs each fact through three exact memory interventions to test whether deletion truly removes it — probing behavioral survival, representational leakage, and adversarial recovery. Provable deletion is a core requirement for AI safety, privacy compliance, and trustworthy AI deployment.

Affiliation

Cornell Natural Language Processing Group

Partners

Keywords

LLMs
NLP
Externalized Memory
Machine Unlearning
Knowledge Editing
Retrieval
Python
PyTorch
CUDA

▸ Research

AI · CS

Aug 2025 – Aug 2026

Tagging the Positron Sky: A Naive Bayes Classifier for β+ Decay

Developed BEvAn, a dedicated β+ decay event classifier for the COSI (Compton Spectrometer and Imager) mission, achieving 98.3–99.6% ROC-AUC across seven high-purity germanium detector geometries. Part of an international NASA project led by the UC Berkeley Space Sciences Laboratory with partners including Northrop Grumman, SpaceX, and the U.S. Naval Research Laboratory. Rooted in the Joliot-Curies’ 1934 Nobel-winning framework of positron emission.

Affiliation

NASA Small Explorers (SMEX) Program / UC Berkeley Space Sciences Laboratory

Partners

Report

In preparation — targeting the American Astronomical Society (AAS)

Keywords

Naive Bayes Classifier
Event Reconstruction
Gamma-Ray Astrophysics
Compton Physics
High-Purity Germanium Detectors
Physics-Informed Machine Learning
Lightweight Models
Python
C++
PyTorch
MEGAlib
Geant4
ROOT

AI · CS

Feb 2026 – Jun 2026

Scenario-Based Compositional Statistical Model Checking for Safety Specifications

Published with UC Berkeley faculty at the International Conference on Runtime Verification 2026. Extended VerifAI, an open-source Berkeley toolkit for testing AI-based systems, to cover safety requirements for self-driving cars that the prior framework could not express. Runs up to 32.3× more test simulations in the same time budget and cuts estimation error from 0.275 to 0.014 in the hardest case. Supported by DARPA, NSF, Nissan, and California PATH.

Affiliation

UC Berkeley

Partners

Report

International Conference on Runtime Verification 2026

Keywords

Compositional Analysis
Statistical Model Checking
DFA
Automata Theory
Markov Chains
Python
VerifAI
MetaDrive
Scenic

AI · CS

Feb 2026 – May 2026

Auditing Forgetting in Limited Memory Language Models

Causal evaluation framework for memory separation in Limited Memory Language Models (Zhao et al., 2025). Decomposes post-deletion correctness into parametric leakage, retrieval-mediated correctness, and retrieval artifacts across 1404 datapoints, six prompt formulations, and thirteen database variants.

Affiliation

UC Berkeley

Partners

Report

arXiv preprint arXiv:2607.00605

Keywords

Machine Unlearning
Knowledge Editing
Causal Inference
Python
PyTorch
CUDA
LLMs
NLP
Slurm
Weights & Biases

AI · CS

Sep 2025 – Dec 2025

Beyond Binary Priorities: Multi-Tier SLA Scheduling for Large Language Model Serving

Multi-priority extension to Llumnix (OSDI 2024) enabling fine-grained SLA differentiation for multi-tenant LLM inference while preserving low tail latency. Achieved up to ~3× P99 latency improvement, with diminishing returns beyond four priority tiers.

Affiliation

UC Berkeley

Partners

Report

arXiv preprint arXiv:2608.16336

Keywords

Priority Scheduling
SLO-aware Scheduling
KV-Cache Management
Live Migration
Tail Latency Optimization
Discrete-Event Simulation
Python
Vidur
LLM Serving
Slurm
Weights & Biases

AI · CS

Jan 2025 – Jun 2025

Deep Learning for Segmentation of Hyperspectral Satellite Images

Trained convolutional neural networks for sea, land, and cloud classification of hyperspectral satellite images from the HYPSO-2 mission. Used NVIDIA GPU cluster acceleration to optimize performance and training speed.

Affiliation

NTNU SmallSat Lab

Partners

Roger Birkeland (Advisor)

Report

Manuscript

Keywords

Hyperspectral Imaging
Semantic Segmentation
Convolutional Neural Networks
Lightweight Models
Earth Observation
Spectral Signatures
Python
PyTorch
CUDA
ENVI 5

▸ Engineering

AI · CS

Mar 2026 – Mar 2026

Type-Aware Hybrid RAG for Factoid QA

Retrieval-augmented QA system over UC Berkeley EECS web content. Built a 192-question benchmark from a crawled 8,417-document corpus, with a RAG pipeline combining BM25 retrieval, type-aware reranking, instruction-tuned generation, and a deterministic extractive fallback.

Affiliation

UC Berkeley

Partners

Report

Manuscript

Keywords

NLP
RAG
LLMs
BM25
BFS Crawl
Query Expansion
Slot Filling
Python
Slurm

Sep 2025 – Dec 2025

Four Stages, Two ISAs: A Pipelined RV32IF Core on PYNQ-Z1 FPGA

Pipelined RISC-V SoC on the Digilent PYNQ-Z1 implementing an RV32I core with CSR support and a pipelined RV32F floating-point unit. Reached 58 MHz with ~1.16 integer CPI, ~1.83 FP CPI, and an FOM of 12.3.

Affiliation

UC Berkeley

Partners

Lawrence Rhee

Keywords

Verilog
Xilinx Vivado
RISC-V
FPGA
PYNQ-Z1
RTL Design
Hardware-Software Co-Design
ISA Compliance Testing

CS · EE

Jun 2025 – Aug 2025

Automated Test-Evaluation System for Automotive Image Sensors

Designed and implemented an automated test-evaluation software system for automotive image sensors, focusing on efficient data storage, repeatable test procedures, and system-level reliability. Output structured in alignment with industry standards such as EMVA 1288 to enable consistent sensor evaluation across revisions.

Affiliation

Sony Europe

Partners

Vegard Havellen (Advisor)

Keywords

Image Sensors
Data Analysis
Data Validation
Python
REST APIs
EMVA 1288
Image Sensors
Docker
Vue
TypeScript
Django
PostgreSQL

Dec 2022 – Feb 2023

End-to-End Client Acquisition System

Custom CRM and client acquisition engine integrating the Brønnøysund Register and three phone registries (1881, 180, Gule Sider) for automated data enrichment and contact verification. Saved ~450 hours/year and reduced third-party API costs by ~$10,000.

Affiliation

BlinkWeb

Keywords

CRM
Data Enrichment
Data Validation
Python
REST APIs
MySQL
Web Scraping

02. Get in Touch

I'm open to interesting conversations and collaborations. Drop me a line and I'll get back to you as soon as possible.

aryar at stud dot ntnu dot no