RISC-V ML Inference Co-Processor for Ultra-Low-Power Wireless SoCs
Extending a custom SystemVerilog pre-processing accelerator for ML into a dedicated inference co-processor, unifying pre-processing and inference in a single peripheral unit to support a parallel RISC-V ML ISA extension. Targeting on-device ML for ultra-low-power wireless SoCs.
Affiliation
Nordic Semiconductor ASA
Keywords
- SystemVerilog
- RISC-V
- ISA Extensions
- Hardware Accelerators
- ML Inference
- On-Device ML
- RTL Design
- Ultra-Low-Power Design
- Hardware-Software Co-Design