Four Stages, Two ISAs: A Pipelined RV32IF Core on PYNQ-Z1 FPGA

This project implements a pipelined RISC-V SoC on the Digilent PYNQ-Z1 FPGA. The core is RV32I with CSR support, paired with a pipelined RV32F floating-point unit.

The four-stage in-order pipeline includes hazard detection, data forwarding, and precise control-flow handling, covering end-to-end hardware-software co-design from RTL to a processor that boots and runs C benchmarks.

The system was verified using the official RISC-V ISA tests and end-to-end workloads executed directly on FPGA hardware. Final numbers: 58 MHz operating frequency, ~1.16 integer CPI, ~1.83 floating-point CPI, and an FOM of 12.3.

Developed within a UC Berkeley hardware course supported by Apple's New Silicon Initiative and co-taught with industry researchers from NVIDIA.