Quantization-Limited SNR on a 12-bit Multi-ADC Pipeline

Introduction

This project is the measurement front-end for a radar/microphone pipeline built around a Raspberry Pi 3B+ and five external Microchip MCP3201 12-bit ADCs sampled in parallel over a shared SPI bus. The Pi has no native analog inputs, so the entire signal-acquisition chain hangs off SPI: a single DMA-driven clock and chip-select line is broadcast to all five ADCs, while each device’s MISO returns on its own GPIO, letting the host capture five simultaneous channels per SPI transaction. The lab was scoped around verifying that the pipeline actually delivers the precision its datasheet promises, quantization-limited SNR at 12 bits is $74\,\text{dB}$, and the question is how close a real, breadboard-mounted, supply-noisy implementation gets to that bound.

Problem Definition

Each ADC samples a continuous voltage $v(t) \in [0,\, V_{\text{ref}}] = [0,\, 3.3]\,\text{V}$ at rate $f_s$ and emits a discrete code $x[n] \in \{0, 1, \dots, 2^N, 1\}$ with $N = 12$. The Nyquist–Shannon condition fixes the upper end of the bandwidth that can be captured without aliasing,

$$f_s \;\geq\; 2 f_{\max},$$

and the resolution of each code is the LSB step

$$\Delta V \;=\; \frac{V_{\text{ref}}}{2^N} \;\approx\; 0.8\,\text{mV},$$

so the worst-case quantization noise amplitude is

$$Q_{\max} \;=\; \frac{\Delta V}{2} \;=\; \frac{V_{\text{ref}}}{2^{N+1}}.$$

For a full-scale sinusoidal input, the theoretical SNR of an ideal $N$-bit ADC is the standard result

$$\mathrm{SNR}_{\text{ideal}} \;=\; 6.02\,N + 1.76\,\text{dB} \;=\; 74\,\text{dB}\;\;\text{at}\;\; N=12,$$

which sets the headline target. The empirical SNR is computed from the measured spectrum as

$$\mathrm{SNR} \;=\; 10 \log_{10}\!\left( \frac{P_{\text{signal}}}{P_{\text{noise}}} \right),$$

with $P_{\text{signal}}$ the energy in the input tone’s bin (and its $\pm f_0$ image), and $P_{\text{noise}}$ the integrated energy across the rest of the spectrum (DC bin excluded, since the DC offset is a deterministic bias rather than noise). The lab’s job is to quantify the gap between $\mathrm{SNR}_{\text{ideal}}$ and the realized $\mathrm{SNR}$ across three input frequencies and to attribute that gap to the dominant noise sources in the chain.

Approach

The pipeline decomposes into four stages: a Raspberry Pi host configured for headless data acquisition, a multi-ADC SPI fan-out with a shared clock and per-channel MISO, an LC supply filter on the 3.3 V rail, and a host-side spectral-analysis pipeline that converts raw codes into SNR figures.

Raspberry Pi Host and SPI Fan-Out

The Pi is flashed with 32-bit Raspberry Pi OS via the Imager (with SSH, hostname, and Wi-Fi pre-configured), reached over SSH for control and SFTP for pulling sample dumps. All five MCP3201s share the SCK and CS lines and differ only in the GPIO their MISO is wired to (GPIO 18, 19, 20, 21, 22). A traditional SPI master would drive each device through its own CS, but the MCP3201 starts a fresh conversion on every CS falling edge regardless of MISO ownership, so a single CS pulse drives all five conversions simultaneously and the host reads the five MISO bits in lock-step. The C client uses pigpio’s rawWaveAddSPI interface, which DMA-bit-bangs the SPI transaction so the bit timings are guaranteed to within roughly $1\,\mu\text{s}$ and the CPU is left free for buffer management. Sample rate is set to $T_p = 32\,\mu\text{s}$, giving $f_s \approx 31\,250\,\text{Hz}$.

LC Supply Filter

ADC resolution is only as good as the stability of $V_{\text{ref}}$ (per the LSB equation above), so the 3.3 V rail is filtered before it reaches VDD and VREF. A second-order LC topology with a $100\,\text{mH}$ inductor and a $100\,\mu\text{F} + 470\,\mu\text{F} + 100\,\text{nF}$ capacitor stack has transfer function

$$H(\omega) \;=\; \frac{\frac{1}{j\omega C}}{\frac{1}{j\omega C} + j\omega L},$$

and at the $-3\,\text{dB}$ point $|H| = \sqrt{2}/2$, which solves to

$$f_c \;=\; \sqrt{\frac{1 + \sqrt{2}}{4\pi^2 C L}} \;\approx\; 36.07\,\text{Hz}$$

with the nominal component values. Each ADC additionally carries two $1\,\mu\text{F}$ decoupling capacitors (one between VREF and IN−, one between VDD and VSS) to suppress the high-frequency switching that the SPI clock and Pi-side DC-DC injects into the rail.

Spectral Analysis and SNR

Each captured channel is windowed with a Hann window

$$w[n] \;=\; 0.5 \!\left[\, 1, \cos\!\left(\frac{2\pi n}{N-1}\right) \right], \qquad 0 \leq n \leq N-1,$$

which is a reasonable default between main-lobe width and side-lobe leakage; Hamming and Blackman were both available but Hann gave the cleanest peak/floor separation for sinusoidal test tones. The windowed sequence is zero-padded from $N$ to $M$ samples,

$$x_p[n] \;=\; \begin{cases} x[n] & 0 \leq n < N, \\ 0 & N \leq n < M, \end{cases}$$

and the DFT is taken on the padded length,

$$X_p[k] \;=\; \sum_{n=0}^{M-1} x_p[n]\, e^{-j\,\frac{2\pi}{M} k n}, \qquad k = 0, 1, \dots, M-1.$$

Padding does not add information but refines the frequency-axis step, which sharpens the visual location of the peak without changing the underlying energy spectrum. The SNR formula above is then evaluated by taking $P_{\text{signal}}$ as the energy in the bins at $\pm f_0$ and $P_{\text{noise}}$ as the energy in every other bin except DC.

Experimental Verification

A 12 V sinusoid with $1\,\text{V}$ amplitude and $1\,\text{V}$ DC offset (so the signal lives in $[0,\,2]\,\text{V}$, comfortably inside the $[0,\,3.3]\,\text{V}$ ADC range) is generated by an Analog Discovery 2 (AD2) and fanned out onto a common IN+ line that all five ADCs share. The same AD2 in impedance-measurement mode is used to characterise the supply filter’s inductor over $100\,\text{Hz}$ to $10\,\text{kHz}$.

Results

The LC filter’s measured frequency response, swept with the AD2, shows the $-3\,\text{dB}$ knee at $26.24\,\text{Hz}$ rather than the predicted $36.07\,\text{Hz}$. Impedance-measuring the inductor across the same sweep gives an averaged inductance of $L = 126.8\,\text{mH}$ versus the nominal $100\,\text{mH}$, which alone shifts the theoretical knee to $32.03\,\text{Hz}$ and explains the bulk of the discrepancy, the residual $\sim 6\,\text{Hz}$ shift is attributable to capacitor tolerance, the inductor’s ESR/DCR, and parasitic effects on the breadboard. A small unexpected secondary knee around $50\,\text{Hz}$ is consistent with mains-frequency pickup or a resonance in the breadboard layout.

The ADC chain was driven with single-tone sinusoids at three frequencies and the SNR computed channel-by-channel. The realized SNR sits about $19\,\text{dB}$ below the 12-bit quantization bound and is essentially flat across the three test frequencies, which is consistent with broadband noise (quantization, supply ripple, and EMI pickup) dominating over any frequency-dependent loss in the analog front-end.

Input tone	Empirical SNR	Theoretical $6.02 N + 1.76$	Gap
$1\,\text{kHz}$	$55.22\,\text{dB}$	$74\,\text{dB}$	$-18.78\,\text{dB}$
$2\,\text{kHz}$	$55.14\,\text{dB}$	$74\,\text{dB}$	$-18.86\,\text{dB}$
$10\,\text{kHz}$	$55.18\,\text{dB}$	$74\,\text{dB}$	$-18.82\,\text{dB}$

The $74\,\text{dB}$ ceiling is itself the quantization-limited SNR: the LSB-floor noise of an ideal 12-bit quantizer, with no other error source present. Hitting it requires that every other contributor, supply ripple, reference drift, EMI pickup, clock jitter, breadboard parasitics, is at least $10\,\text{dB}$ below the quantization floor. The observed $\sim 55\,\text{dB}$ is therefore not a quantization-noise problem in any direct sense; quantization sets the optimistic ceiling, and the gap is entirely additive noise on top of that ceiling. The frequency-flatness of the gap across $1$, $2$, and $10\,\text{kHz}$ is consistent with this: quantization noise is white in expectation, and so is broadband supply/EMI noise, so neither has a fingerprint that would single it out from the others without injecting a known disturbance and measuring the SNR delta.

Time-domain plots of all five channels for the $1\,\text{V}$-amplitude $1\,\text{V}$-offset test tone show identical waveforms with the correct frequency and shape, but with a systematic offset: the peaks sit slightly above $2\,\text{V}$ and the troughs slightly above $0\,\text{V}$, indicating a small, channel-independent bias on the measured DC level. Because the bias is identical across all five ADCs, it is a property of the measurement chain (reference, input impedance, breadboard drop) rather than of any individual MCP3201.

Future Work

The $19\,\text{dB}$ gap between empirical and quantization-limited SNR is the headline number to attack. Three classes of fix change the cost/benefit calculation differently. First, the analog front-end is currently a breadboard with long jumper wires and shared rails, which makes it a near-perfect aerial for EMI from the bench environment and the Pi’s own switching regulators; lifting the design onto a soldered PCB with a continuous ground pour, short trace runs, and shielded analog islands is the single largest available improvement and would also resolve the unexplained $50\,\text{Hz}$ knee in the filter response. Second, the LC filter as built has a real inductance $27\,\%$ above nominal, which both shifts the cutoff and adds DCR-driven attenuation in the passband, replacing the $100\,\text{mH}$ inductor with a tighter-tolerance part (or characterising the actual $L$ before laying out the filter) removes a contributor to in-band signal loss that directly drags $P_{\text{signal}}$ down in the SNR ratio. Third, a more stable voltage reference (a dedicated $\text{LDO}$ or precision reference rather than the Pi’s 3.3 V rail) tightens $V_{\text{ref}}$ and therefore tightens the LSB, which removes a multiplicative noise term that the current rail leaves on the table.

The systematic offset visible in every ADC time series is a separate problem and a much cheaper one to solve. Because the offset is identical across channels and stable across runs, it can be measured once at calibration time (drive a known $V_{\text{cal}}$ into IN+, read all five codes, store the per-channel offset $\hat{b}_i$) and subtracted in software during post-processing. Texas Instruments publishes a standard recipe for this kind of two-point ADC calibration; folding it into the existing Python pipeline is a few lines of code and removes a bias that currently has to be accounted for downstream every time the system is used.

A more fundamental redesign for the next iteration is to replace the bit-banged SPI master with the Pi’s native hardware SPI peripheral. The DMA-bit-banged path was chosen because it lets five independent MISO lines be sampled in lock-step on a controller that has only one hardware SPI peripheral, but it costs a non-trivial amount of CPU bandwidth in rawWaveAddSPI setup and limits the maximum sustainable sample rate well below what the MCP3201 datasheet permits ($100\,\text{ksps}$ at $V_{\text{DD}} = 2.7\,\text{V}$, faster at $3.3\,\text{V}$). Moving to a multi-channel ADC (or to a Pi 4/5 with multiple hardware SPIs) lifts that ceiling and pushes the project toward the radar/microphone sample rates the eventual application needs.